1. Field of the Invention
The present invention relates generally to methods for fabricating integrated circuits using complementary metal oxide semiconductor (CMOS) technology. More particularly, the present invention relates to methods and devices for implementing CMOS technology while maintaining balance between p-channel and n-channel transistors when operated at reduced voltage supplies.
2. State of the Art
There has been a relatively recent trend to reduce the power supply voltage for CMOS devices. For example, when using CMOS transistors in battery powered environments, it is desirable to decrease power consumption by decreasing the voltage power source from, for example, 5 volts to 3 volts. Further, decreased voltage power sources are desirable for providing smaller CMOS technologies (i.e., reduced size transistors require decreased voltage power sources to avoid transistor damage).
One conventional technique for fabricating CMOS transistors which accommodates the need for reduced size transistors involves using low dose drain (LDD) technology, also referred to as lightly doped drains. LDD technology was created to reduce the hot electron effect which degrades the performance of relatively small transistors having short channels (i.e., transistor gates which are less than or equal to 1.2 microns in length). Unlike conventional transistors where the source and drain implant regions are self-aligned to the edge of a polysilicon gate, an LDD transistor has two low dose regions which are implanted in the substrate in alignment with the gate. Spacers are formed on the substrate adjacent to the gate, with the source and drain implant regions being displaced from the gate edge by the width of the spacers. FIG. 1D shows an n-channel transistor and a p-channel transistor formed in a common substrate, each of the transistors having low dose drain regions.
A typical process for forming the FIG. 1D transistors will be described with reference to FIGS. 1A to 1D. FIG. 1A illustrates a substrate 100 of a first conductivity type (e.g., p-type material) having a well region 102 formed with material of a second conductivity type (e.g., n-type material). An n-channel transistor is formed with lightly doped regions 104 and 106 of n-type material. A p-channel transistor is formed with lightly doped regions 108 and 110 of p-type material. The n-channel and p-channel transistors have gates 112 and 114, respectively. The gates are formed, for example, of polysilicon over a gate oxide 116.
Referring to FIG. 1B, a uniform layer of oxide 118 can be formed over the n-channel and p-channel transistors. The oxide 118 provides a layer from which spacers can be etched to displace the source and drain implant regions from the edges of the gates 112 and 114.
Referring to FIG. 1C, a blanket etch can be used to form the spacers 120 and 122 of the n-channel transistor at the same time spacers 124 and 126 are formed for the p-channel transistor. The uniform layer of oxide 118 from which the spacers are formed can, for example, be a material such as TEOS.
Referring to FIG. 1D, the spacers 120 to 126 are used to define the edge of the source and drain regions relative to the edge of the gate in each of the p-channel and n-channel transistors. Using the spacers, n + source and drain regions 128 and 130 can be formed with respect to the n-channel transistor. The p-channel transistor can be masked during formation of the source and drain regions in the n-channel transistor. Afterward, source and drain regions 132 and 134 can be formed for the p-channel transistor, with the n-channel transistor being masked. Thus, conventional techniques result in n-channel and p-channel transistors being configured with similarly sized LDD regions of equally dosed material.
Despite the advantages which can be realized by reducing the voltage power source (e.g., reduced power consumption and reduced size), significant complications can result from operating CMOS transistors designed for operation at a higher voltage source with a reduced voltage power source.
Unbalanced operation among p-channel and n-channel transistors can occur when the voltage power source is reduced. For example, 3 volt operation of CMOS technology designed for 5 volt operation can result in unbalanced operation among n-channel transistors relative to p-channel transistors. This is because n-channel transistors degrade differently than p-channel transistors when the voltage power source is reduced. FIG. 2 shows the relative degradation of current drive versus supply voltage for n-channel and p-channel transistors. The current drive of a p-channel transistor designed for operation with 5 volts, but actually operated at 3 volts, is decreased by 60%. The current drive of similarly operated n-channel transistor is decreased by only 50%. Thus, balanced current ratios of I.sub.p-h :I.sub.n-ch =1:1 for a 5 volt power source (where I.sub.p-ch is the current drive of a p-channel transistor and I.sub.n-ch is the current drive of an n-channel transistor) can become unbalanced when a 3 volt power source is used. The current ratios of these transistors when operated with a 3 volt power source can be 0.8:1. This unbalanced operation among n-channel transistors and p-channel transistors can lead to significant timing errors when the transistors are used in a high speed circuit.
To illustrate circuit timing errors due to an unbalance among n-channel transistors and p-channel transistors, consider using an n-channel pull-up transistor in conjunction with a p-channel pull-down transistor. Here, both the n-channel transistor and the p-channel transistor have their gates tied together. When the pull-up and pull-down transistors are operated at the reduced voltage power supply of 3 volts, the unbalanced degradation of the p-channel and n-channel CMOS transistors will render the pull-up weaker (i.e., slower) while the pull-down will remain unaffected. If these CMOS transistors are relied upon for triggering a subsequent event, the relatively slow pull-up can detrimentally affect the triggering of subsequent transistors, and throw off timing within the integrated circuit. FIG. 3 shows an inverter circuit and a relative change in output pulse shape due to reduced supply voltage.
To address this problem, the entire integrated circuit can be redesigned to accommodate operation at the reduced voltage power source. As referenced herein, the term "redesign" can include appropriate sizing of n-channel transistor gates relative to p-channel transistor gates prior to circuit fabrication. The current drive, I.sub.drive, between the source and drain of a CMOS transistor is proportional to gate width (G.sub.w) divided by gate length (G.sub.l); that is, I.sub.drive is proportional G.sub.w /G.sub.l. Thus, either Gw can be increased or G.sub.l can be decreased to increase current drive of a p-channel transistor and balance its operation with the current drive of an n-channel transistor in the integrated circuit. Alternately, the gate of an n-channel transistor can be modified to balance the current drive of the p-channel transistors.
However, difficulties are encountered when attempts are made to increase or decrease relative gate sizes of p-channel and n-channel transistors. Gate lengths of typical CMOS transistors are already extremely small (e.g., on the order of 0.8 microns). Adjusting the relative gate sizes to achieve accurate balance between n-channel and p-channel transistors can therefore be complex, costly and impractical. Gate widths are typically larger than gate lengths, making them easier to adjust. However, a significantly increased gate width can be required to achieve the necessary balance. This resultant increase in transistor size can require a relayout of all transistors in the integrated circuit. This relayout process can also be complex, costly and possibly prohibitive if the overall integrated circuit chip size exceeds customer specifications.
Accordingly, it would be desirable to achieve the benefits of operating CMOS logic which has been designed for operation with a first voltage, at a second voltage (e.g., a relatively low voltage) without unbalancing operation among n-channel and p-channel transistors. By avoiding the possible occurrence of unbalanced operation, any need to redesign an integrated circuit containing such transistors, and any need to initiate a relayout of any such integrated circuit are avoided. It would also be desirable to provide a process of maintaining balanced operation which is relatively simple and straightforward, and which will not introduce increased fabrication complexity. Further, any such process should not detrimentally affect the speed of circuit operation, or detrimentally affect the operating characteristics of transistors by forcing their operation in a dangerous (e.g., unstable) region.